The present invention relates generally to optimized adders, and more specifically to three-state binary adders with endpoint correction for use in pipelined analog-to-digital converters.
Conventional data conversion devices often include an analog-to-digital converter (xe2x80x9cADCxe2x80x9d).
ADCs operate primarily to quantize analog data signals for use in digital signal processing. In recent years, the need for more powerful digital signal processing systems has continued to increase, thereby requiring higher resolution and more accurate ADCs.
Conventional ADCs have commonly employed switched capacitor elements and differential amplifiers. These switched capacitor elements, in order to obtain the necessary accuracy, must be accurately matched, thereby requiring the manufacturing process to achieve high levels of accuracy, which may be difficult due to matching limitations between components. Since these limitations commonly exceed manufacturing process capabilities, various calibration techniques have been implemented.
Conventional ADCs address various ones of the above-noted disadvantages. One such conventional ADC is known as a xe2x80x9cpipelined ADC.xe2x80x9d A pipelined ADC operates to convert an analog signal received at the input of a pipeline of xe2x80x9cnxe2x80x9d stages into an xe2x80x9cnxe2x80x9d-bit digital output signal. Each converter stage is, essentially, a sub-ADC and a reconstructing digital-to-analog converter (xe2x80x9cDACxe2x80x9d).
For instance, in a typical pipelined ADC, a xe2x80x9cfirstxe2x80x9d stage receives the analog input voltage and, in response to the analog level, converts the same to generate the most significant bit (xe2x80x9cMSBxe2x80x9d) of the resulting digital signal. Subsequent stages in turn refine the determination of the value of the signal, producing additional bits in less significant positions of the resulting digital signal.
More specifically, an initial xe2x80x9ccoarsexe2x80x9d conversion of a voltage VIN is made by a nth-bit sub-ADC, which coarse conversion is a nth-bit approximation of the input voltage VIN. Commonly, a nth-bit DAC converts this nth-bit digital approximation back into an analog signal, which represents the xe2x80x9ccoarsexe2x80x9d nth-bit approximation of the input voltage VIN. This xe2x80x9cnth-bitxe2x80x9d analog signal is then subtracted from the actual input voltage VIN, and the resulting remainder, or xe2x80x9cresidue,xe2x80x9d of the first nth-bit conversion represents the residual portion of the input voltage VIN that was not accurately converted by the nth-bit sub-ADC.
This residual portion is amplified to enlarge the conversion range for a second or xe2x80x9cfinerxe2x80x9d conversion performed by a mth-bit sub-ADC. This xe2x80x9cfinerxe2x80x9d mth-bit digital approximation of the input voltage VIN by the mth-bit sub-ADC is passed to an adder where it is added to the xe2x80x9ccoarsexe2x80x9d nth-bit conversion previously performed by the nth-bit sub-ADC.
This multi-stage process is repeated until the pipeline is complete, with the residue of each stage being amplified and quantized by the following stage. The limiting example of such an extension is a one-bit-per-stage architecture, which requires only one comparator per added bit of resolution desired. The gain of the inter-stage amplifier is set such that coarse and fine conversions have a one-bit overlap so as to allow for the correction of errors made in the coarse conversion.
Multi-stage pipeline ADC architectures provide a scalable approach that reduces significantly the total number of comparators required to perform a conversion. This reduction in the number of required comparators results in a significant die area and power consumption savings for the ADC.
Traditional correction logic in a pipelined ADC is implemented as xe2x80x9cfullxe2x80x9d addition and carry over of the overlapping correction bits from each stage. One traditional approach, known as the threshold limit algorithm, has theoretical trip voltages for a two bit sub-converter of xc2x1xc2xd full scale and zero, and has an error tolerance of zero.
Another contemporary approach, known as the compensated algorithm, improves the margin of error relative to the threshold limit algorithm by increasing the two-bit subcomparator trip points to xc2x1xc2xe full scale. The added xc2x1xc2xc full scale offset allows for an improved error margin relative to the threshold limit algorithm. This offset, however, translates into a differential non-linearity (xe2x80x9cDNLxe2x80x9d) error of xc2xc of the least significant bit at codes 1 and (2nxe2x88x922).
Unfortunately, both of these algorithms suffer non-monotonic error throughout the conversion range when the error constraints are not met.
A need therefore exists in the art for a binary adder that further increases the efficiencies of pipelined ADCs and reduces the die area and power consumption requirements of the ADC. A further need exists for a three-state binary adder that eliminates the logic necessary for a xe2x80x9c11xe2x80x9d state in pipelined ADCs. A yet further need in the art exists for an algorithm that eliminates both DNL error and non-monotonicity problems in endpoint correction.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide optimized adders and, more specifically, three-state binary adders with endpoint correction for use in pipelined analog-to-digital converters. According to one advantageous embodiment, for use in a digital signal processing system, a pipelined analog-to-digital converter is introduced comprising an adder and endpoint correction circuitry. The adder is operable to add received signals. The endpoint correction circuitry, which is associated with the adder, is operable to (i) use xc2x1xc2xd fill scale trip voltages and to (ii) generate over and under indicators.
Important aspects of the principles of the present invention, include that use of three-state binary adders in pipelined analog-to-digital converters, as well as other digital signal processing systems, is easily scalable, significantly reduces delay, and requires less area than an overlapping adder using standard full-adder and half-adder cells. Further, the endpoint correction algorithm hereof eliminates both DNL error and non-monotonicity problems in endpoint correction.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.